1. Field of the Invention
The present invention relates in general to a method of a deep trench capacitor fabrication, and in particular, to a method of selectively etching a HSG (hemispherical Silicon Grain) layer in a deep trench capacitor.
2. Description of the Related Art
DRAM capacitors generally consist of two electrodes isolated by an insulating material. The electrical charge capability of DRAM is determined by the thickness of the insulating material, the surface area of the electrodes and the electrical properties of the insulating material. As ICs become more compact, semiconductor designs have reduced device dimensions which increase density to accommodate a large number of memory cells. Conversely, memory cell electrodes must provide sufficient surface area for electrical charge storage. Furthermore, high dielectric constant (high k) dielectric materials are adopted to increase the capacitance of the memory cells, in addition, as DRAM becomes more compact, deep trench type capacitors are widely used to increase surface area. Hence, HSG technology is used to increase the surface area of the electrode plate of the trench capacitor. U.S. Pat. Nos. 6,177,696, 6,537,872 and 6,555,430 disclose applications for forming HSG on a trench-type capacitor.
In FIG. 1A, a semiconductor substrate 10 having a pad oxide layer 12, a pad nitride layer 14, a deep trench DT, a collar dielectric layer 16 on the upper sidewall of the deep trench DT, and an etch stop layer 15 on the sidewall and bottom of the deep trench, such as an oxide layer is provided.
Next, in FIG. 1B, an amorphous silicon (α-Si) layer 17 is formed on the etch stop layer 15. In FIG. 1C, a doping dielectric layer is formed on the α-Si layer 17, with the proper concentration, flow rate and time. The α-Si layer 17 then forms a HSG layer 22 in-situ, increasing the surface area of the trench DT.
Subsequently, in FIG. 1D, a first resist layer 26 is filled into the deep trench DT, and recessed to a predetermined depth of the lower of the deep trench DT. Then, using the recessed resist 26 as an etching mask, the HSG layer 22 in the upper portion of the deep trench is etched. Since the etching selectivity of the deep trench silicon substrate to the HSG layer is very low, when etching the HSG layer 22, the etch stop layer 15 is required as a buffer to insulate and protect the deep trench silicon substrate. Next, in FIG. 1E, the etch stop layer 15 in the upper portion of the deep trench DT is etched, and the first resist layer 26 is then removed from the deep trench DT.
Next, in FIG. 1F, an ASG layer 28 is formed on the bottom and sidewall of the deep trench DT, then a second resist layer 30 is formed on the ASG layer 28 and recessed to a predetermined depth in the lower portion of the deep trench DT. Subsequently, in FIG. 1G, using the recessed second resist layer 30 as an etching mask, the ASG layer 28 in the upper portion of the deep trench DT is etched, and the second resist layer 30 is then removed.
In FIG. 1H, a cap oxide layer 32 is formed in the bottom and on the sidewall of the deep trench, subsequently, In FIG. 1I, a thermal process is performed to diffuse the As+ out of the ASG layer 28 to the lower area of the deep trench DT, forming an n+-type diffusion area 34 to serve as a buried plate 34 of the deep trench capacitor 36. Finally, the ASG layer 28 and the cap oxide layer 32 are etched and removed from the deep trench DT, accomplishing fabrication of the deep trench capacitor 36 with HSG layer.
The above described conventional fabrication steps are complicated, requiring not only two steps of resist coating/recessing, but also an additional etching stop layer to insulate the HSG layer and the deep trench silicon substrate. The purpose of the above processes is to prevent direct formation of the HSG layer on the upper sidewall of the deep trench, such that the HSG layer and the silicon substrate of the deep trench do not make contact. The reason being the single crystal silicon substrate is very similar to the HSG layer in physical properties, so that the etching selectivity of the both is nearing the same, resulting in damage to the silicon substrate when the HGS layer is etched, and further, extending the deep trench, resulting in sub-threshold voltage (sub-Vt) leakage.
The above process uses an etching stop layer formed between the silicon substrate and the HSG layer to overcome the problem, however, the process is too complicated, and, the etching stop layer will form a parasitic capacitance within the buried plate at the lower of the deep trench, impacting the capacitance of the capacitor as a result.